1. Field of the Invention
This invention relates to voltage-controlled oscillators (VCO), and more particularly, to a voltage-controlled oscillator which is specifically used in a phase-locked loop (PLL) circuit, capable of minimizing the phase disturbance in the output frequency of the PLL circuit due to noise input to the VCO.
2. Description of Related Art
The voltage-controlled oscillator (VCO) is a core device in conventional phase-locked loop (PLL) circuits. With integrated circuits getting more complicated, the noise level in the source voltage is usually high. This noise, when input to the VCO in the PLL circuit, would cause a phase disturbance to the output frequency, causing the output frequency to be inaccurate.
FIG. 1 is a schematic block diagram of a conventional PLL circuit. As shown, the PLL circuit includes a first frequency divider 10, a phase comparator 12, a loop filter 14, a VCO 16, and a second frequency divider 18. The first frequency divider 10 receives an external clock signal V.sub.S and generates an output clock signal V.sub.I whose frequency is 1/M of the frequency of the input clock signal V.sub.S. The phase comparator 12 has two input ends: a first input end receiving the clock signal V.sub.I and a second input end receiving a reference signal V.sub.C which is a feedback signal obtained by processing the output V.sub.O of the PLL circuit through the second frequency divider 18. The phase comparator 12 compares V.sub.I with V.sub.C to thereby generate an output signal V.sub.D in such a manner that, when V.sub.I &gt;V.sub.C, the output signal V.sub.D is a high voltage level representing a first binary value, for example 1; and when V.sub.I &lt;V.sub.C, the output signal V.sub.D is a low voltage level representing a second binary value, for example 0. the output signal V.sub.D is therefore a binary data stream which is transferred subsequently to the loop filter 14 where it is integrated to obtain an analog output voltage V.sub.G. This analog output voltage V.sub.G is transferred to the VCO 16 to cause the VCO 16 to output an oscillating signal V.sub.O with a frequency proportional to the magnitude of the voltage V.sub.G. This oscillating signal V.sub.O is taken as the output of the PLL circuit. Also, the oscillating signal V.sub.O is fed back through the second frequency divider 18, where it is decreased in frequency. The output of the second frequency divider 18 then serves as the above-mentioned reference voltage V.sub.C to the phase comparator 12.
Assume that the variation of the voltage V.sub.G input to the VCO 16 is .DELTA.V and the variation of the output frequency f in response to .DELTA.V is .DELTA.f, then the gain G of the VCO 16 is defined as follows: EQU G=.DELTA.f/.DELTA.V
Conventional PLL circuits have a typical gain of about 100 MHz/V (megahertz/volt). When a noise appears in the input to the VCO, for example a 10 mV (millivolt) noise, it will cause the output frequency to have a phase disturbance of 5 mV.times.100 MHz/V=500 kHz (kilohertz). This high phase disturbance is undesired.